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authorEkaitz Zarraga <ekaitz@elenq.tech>2024-11-18 21:08:41 +0100
committerEkaitz Zarraga <ekaitz@elenq.tech>2025-01-29 14:53:04 +0100
commit7c20ba77672df6a5d6f8ffc6aab00b5693087f92 (patch)
tree24a42586de55fb23ee3a06623b693fb550356abb /lib/btowc.c
parentce8b8e4778e7e757855d4397626228ae0f1979f3 (diff)
downloadguile-7c20ba77672df6a5d6f8ffc6aab00b5693087f92.tar.gz
riscv: float/double call convention implementation
RISC-V uses a0-a7 registers for argument passing. Float/double arguments use f0-f7 first and continue in a0-a7 if needed. Once registers are consumed, stack is used. This commit changes how lightening passes arguments in order to allow this behavior.
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